Numerous structures for integrated npn transistors are known which call for creation of a lateral dielectric insulation by selective thermal oxidation of a silicon substrate.
The transistors manufactured in accordance with this selective oxidation technique are able to reach very high cutoff frequencies even on the order of GHz.
It is known that high-frequency performance is limited by the base distributed resistance (rbb') and by the parasite capacitances associated with the collector junction (Cc) and the emitter junction (Ce).
Known structures fall into three classes, i.e. (a) transistors with low Cc and high rbb', (b) transistors with high Cc and low rbb', and (c) transistors with intermediate Cc and rbb' values.
A structure of type (a) is proposed for example by Ko and others and described in the journal "IEEE Transactions on Electron Devices" of March 1983.
A manufacturing process conceived to reduce the number of process and masking steps for said structure is described.
In accordance with said process a substrate of p silicon is oxidized and, with a mask, a buried layer is produced which is then subjected to antimony diffusion. On the substrate thus treated is grown an epitaxial layer on which is grown a thin layer of thermal oxide and silicon nitride is deposited. An oxide insulation is formed by silicon etching, field implanting and oxidation. Then a self-aligning mask is applied to determine the contact areas of the transistor by selectively removing the nitride layer. The exposed area is oxidated to form a self-aligning oxide layer. The nitride layer is subsequently removed. The collector contact region is created by phosphorus implantation and the base region by boron implantation.
After removal of the photoresist the emitter mask is applied to determine the emitter implantation region. The photoresist is then removed and a single thermal cycle is performed for annealing and penetration of the base and emitter implantations. The self-aligning diagram used produces with each contact thin layers of oxide which are removed by short open sky etching. Lastly follows evaporation of the metal.
The shortcoming of this structure is that the region separating the base contact from the "intrinsic" base (the base region under the emitter), hereinafter called extrinsic base region, is a high-resistivity region because the oxide present over this region partially screens the boron implantation of the base.
In other type (c) structures, before oxidizing the areas not covered with nitride, boron is implanted. Precisely, as described in U.S. Pat. No. 4,199,380, an oxidation resistant layer (Si.sub.3 N.sub.4) is applied on a layer of thermal oxide grown on the epitaxial layer. Self-aligning openings are created in said resistant layer to expose portions of the epitaxial layer. Said openings determine the spaces between the contacts of the active elements of the circuit. Impurities of a first type (boron) are then applied through a subsequent masking to form the basic extrinsic region in a portion of said silicon substrate. Then the silicon zones are oxidized to form a layer of relatively thick self-aligned oxide. The oxidation resistant layer is then removed to expose those portions of the epitaxial layer where the active regions are to be formed. Appropriate doping impurities are applied to form the intrinsic base region, the emitter regions and the collector contact regions. Then the implantations of said impurities are redistributed by means of thermal cycles.
The shortcoming which occurs in this structure is that the extrinsic base region sees the growth of a quite thick oxide layer which reduces considerably the boron concentration near the silicon/silicon oxide interface because of segregation of the boron in the oxide. This circumstance increases the value of the rbb' and can also originate inverted surface layers. In addition, the depth of the junction of the extrinsic base region is greater than that of the intrinsic base and this produces an increase of the Cc.
In type (b) structures, in addition to recording very high values for both the capacitances Cc and Ce, a decrease in the current flow is brought about. Indeed, the breakdown of the collector junction is caused by the minimum thickness of the low-concentration collector while the current flow is inversely proportionate to the low-concentration collector under the intrinsic base. In this type of transistor the low-concentration collector under the intrinsic base is always thicker than elsewhere. This effect is also present in type (c) structures although in a less pronounced manner.
In all the known structures described there is also the possibility of short circuits induced by the metallization between the emitter and base regions as a result of the contact opening process.
From the art there is also known a manufacturing process for a bipolar npn transistor which uses a thick layer of silicon dioxide to insulate the transistor.
The starting material is a lightly doped type p silicon substrate which is oxidized and in which is produced a buried layer; then a type n epitaxial layer is grown. On the latter layer is grown a layer of silicon dioxide on which is then deposited a layer of silicon nitride. Then masking and etching of the nitride and oxide layers and of the silicon itself are performed to approximately half of the epitaxial layer. At this point boron is implanted. The resist is removed and the wafers are oxidized so that all the remaining epitaxial layer not protected by the nitride is converted into silicon dioxide. At this point the nitride is totally removed. The base can be implanted through the oxide. The contact areas of the base, emitter and collector regions can be determined simultaneously with a single mask. While the emitter and collector contact regions are implanted, a mask is used to protect the base contact area. After the emitter has been implanted it is brought to the desired depth in a nonoxidizing environment. The thin oxide which is formed on the emitter, base and collector contacts can be removed in a dilute solution of hydrofluoric acid.
After removal of the thin oxide a new layer of silicon nitride can be deposited on the wafer to protect the device from contaminating ions. This layer can be selectively anodized to avoid resorting to a further photolithographic process to open the contact regions.
Summing up, the transistors obtained by the above process present the following shortcomings. (1) the base region does not have uniform junction depth and consequently the junction is not completely flat and has high Cc, (2) the current flow is not maximal since the junction of the extrinsic base region is deeper than that of the intrinsic base, (3) segregation of the boron occurs in the oxide (type c structure), (4) the boron concentration increases in the region between the intrinsic and extrinsic bases (type b and c structures), and (5) etching of the thin oxide which forms after diffusion of the emitter creates short circuit problems between the emitter and the base induced by the metallization.